![]() ![]() These new technologies, which result from the strategic partnership between the companies, will help provide a PPA boost for designs on TSMC's N3 process. To support TSMC's ultra-low-voltage design closure, the Synopsys optimization engine has been improved to use new footprint optimization algorithms. The platform has been enhanced to deliver improved synthesis and global placer engines that optimize library cell selection and placement results. The digital design flow, anchored by the tightly integrated Synopsys Fusion Design Platform ™, features new technologies to ensure faster timing closure, full-flow correlation from synthesis to place-and-route to timing, as well as physical signoff. "Through our strategic collaboration, we are enabling our customers to achieve next-generation HPC, mobile, 5G and AI designs and quickly launch their product innovations to the market." "We're pleased to see the results of our multi-year collaboration with Synopsys and the certification of their design platform solutions on TSMC's most advanced processes that deliver optimized PPA," said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. ![]() In addition to this certification, Synopsys' digital and custom design platforms have also been certified for TSMC's N4 process. The certification with rigorous validation, based on TSMC's latest version of the design rule manual (DRM) and process design kits (PDKs), is the result of a multi-year collaboration between the two companies. (Nasdaq: SNPS) today announced that TSMC has certified the Synopsys digital and custom design platforms for TSMC's 3nm technology. ![]() 20, 2021 - In a continuing effort to optimize power, performance and area (PPA) for next-generation system-on-chips (SoCs), Synopsys, Inc. The Platforms Optimize PPA for Next-Generation HPC, Mobile, 5G and AI Designs ![]()
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